(1) Field of the Invention
The invention relates generally to the manufacture of very high integrated circuits and more particularly to methods for forming patterns of N well and P well in a silicon substrate in ways that minimize counterdoping.
(2) Description of the Prior Art
In the formation of complimentary devices, such as complimentary metal oxide semiconductor, CMOS field effect transistor integrated circuits in a silicon semiconductor substrate it is required to provide regions in the substrate tailored for the each type of transistor. For example, in the case of CMOS field effect transistor integrated circuits, the P channel devices must be located in regions having an N type doping and the N channel devices must be located in regions having a P type doping. There are three approaches to forming the two different substrate doping, which are referred to as P tub or well, N tub or well, and twin tub or well processes.
The most preferred of the three processes is the twin tub or well process, particularly in the era of very high density integrated circuits with feature sizes of one micrometer or below. In general, the advantage is that the process allows the doping profile in each tub or well region to be independently tailored for optimum device characteristics. The substrate itself can be either lightly doped P or N type.
Workers in the art have been active in developing twin tub or well processes. Some of the patents and publications which are considered significant include Davies et al U.S Pat. No. 4,420,344; Schwabe et al U.S. Pat. No. 4,434,543; Hillenius et al U.S. Pat. No. 4,554,726; Pfiester U.S. Pat. No. 4,847,213; and S. Meguro et al entitled "Hi-CMOS III Technology" published in IEDM 84 pages 59-62 CH2099-0/84/0000-0059 1984 IEDM.
A major problem in the twin tub or well processes involve the overlapping of the tub or well patterns of P and N doping types. The compensation degree has adverse effects on the device formed in the twin wells, especially on the latch-up protection of CMOS circuits.
Neppl et al U.S. Pat. No. 4,803,179 has observed the counterdoping problem and has proposed a process to overcome this problem. They use an undercutting etch technique of the silicon nitride layer located under a photoresist mask which defines the well region. Their preferred process of FIG. 6 through 10 uses a polysilicon layer between their silicon nitride layer and the silicon oxide layer. To ion implant through the polysilion will require a specialized high energy implanter.
It is therefore an object of this invention to provide a process that overcomes or minimizes the counterdoping of the twin well structures of the prior art by simpler procedures.
It is a further object of the invention to provide a process that overcomes or minimizes the counterdoping of adjacent P and N wells by use of an improved mask undercut technique in the polycrystalline silicon layer under the silicon nitride layer and to allow the use of conventional low energy implantation equipment.